Flash memory devices (e.g., NAND, NOR, etc.) have developed into a popular source of non-volatile memory for a wide range of electronic applications. Non-volatile memory is memory that can retain its data values for some extended period without the application of power. Flash memory devices typically use one-transistor memory cells. Changes in threshold voltage of the cells, through programming (which is sometimes referred to as writing) of charge-storage structures (e.g., floating gates or charge traps) or other physical phenomena (e.g., phase change or polarization), determine the data value of each cell. Common uses for flash memory and other non-volatile memory include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, mobile telephones, and removable memory modules, and the uses for non-volatile memory continue to expand.
A NAND flash memory device is a common type of flash memory device, so called for the logical form in which the basic memory cell configuration is arranged. Typically, the array of memory cells for NAND flash memory devices is arranged such that the control gate of each memory cell of a row of the array is connected together to form an access line, such as a word line. For example, a row of memory cells might be those memory cells commonly connected to an access line. Columns of the array might include strings (often termed NAND strings) of memory cells connected together in series between a pair of select transistors, e.g., a source select transistor and a drain select transistor. Each source select transistor is connected to a source, while each drain select transistor is connected to a data line, such as bit line. For example, as used herein when elements are connected they are electrically connected, e.g., by means of an electrically conductive path. As used herein, when elements are disconnected, for example, they are electrically disconnected (e.g., electrically isolated) from each other.
A “column” may refer to memory cells that are commonly connected to a data line. It does not require any particular orientation or linear relationship, but instead refers to the logical relationship between memory cell and data line. A row of memory cells can, but need not, include all memory cells commonly connected to an access line. A row of memory cells might include every other memory cell commonly connected to an access line. For example, memory cells commonly connected to an access line and selectively connected to even data lines may be a row of memory cells, while memory cells commonly connected to that access line and selectively connected to odd data lines may be another row of memory cells. Other groupings of memory cells commonly connected to an access line may also define a row of memory cells. For certain memory devices, all memory cells commonly connected to a given access line might be deemed a physical row, while those portions of the physical row that are read during a single read operation or programmed during a single program operation (e.g., even or odd memory cells) might be deemed a logical row, sometimes referred to as a page.
Some memory devices might include stacked memory arrays, e.g., often referred to as three-dimensional memory arrays. For example, a stacked memory array might include a plurality of vertical strings (e.g., NAND strings) of memory cells, e.g., connected in series, between a source and a data line. The term vertical may be defined, for example, as a direction that is perpendicular to a base structure, such as a surface of an integrated circuit die. It should be recognized the term vertical takes into account variations from “exactly” vertical due to routine manufacturing and/or assembly variations and that one of ordinary skill in the art would know what is meant by the term vertical.
In some examples, a vertical string of memory cells might be adjacent to (e.g., on) a vertical semiconductor, e.g., that might be referred to as a vertical pillar. For example, activation of memory cells in the vertical string may form a conducting channel region in the pillar adjacent to those memory cells. Respective ones of a plurality of access lines might be respectively connected to respective ones of the memory cells in the vertical string. Each of the access lines might be commonly connected to a memory cell in each of a plurality of vertical strings, where the vertical strings of the plurality of vertical strings might be respectively adjacent to pillars, for example. That is, there might be a plurality of pillars and a plurality of memory cells along an access line.
An access line might be connected to voltage-generation circuitry, such as a charge pump, that might generate a program voltage to be supplied to the memory cells commonly connected to the access line. However, voltage delays, e.g., due to resistive and/or capacitive effects (e.g., that might be referred to as an RC delays) between the voltage-generation circuitry and the access line might result in a lower program voltage at the access line than is generated by the voltage-generation circuitry. There may be additional voltage delays along the access line, e.g., due to the RC of the access line and/or the resistance and/or the capacitance of the pillars, that may cause a reduction in the program voltage along the access line, for example.